1. Field of the Invention
The present invention generally relates to a circuit layout structure and a method to scale down an integrated circuit layout. In particular, the present invention relates to a circuit layout structure with substantially different regional line width as well as a method to scale down an integrated circuit layout without substantially jeopardizing the electronic characteristics of devices.
2. Description of the Prior Art
In order to accommodate most semiconductor devices on a limited chip area to lower down the production cost, persons skilled in the art come up with many semiconductor methods to make the size of the devices smaller and smaller so as to make the IC density greater and greater. On one hand, smaller devices facilitate the operational speed, and on the other hand smaller devices reduce the power consumption of the devices. Accordingly, various solutions to scale down the circuit layout structure are practiced by persons skilled in the art.
Generally speaking, scaling down devices after the scale-down requires a substantially change in the IC layout. In such a way, even a simplest scale-down procedure makes the IC layout no longer useful and a new IC layout must be redesigned. It is well known that the design of the IC layout is very expensive and time-consuming.
In order to avoid all the costs for redesigning the IC layout, a method to directly scale down an original IC layout to obtain an IC layout of the required shrunk size has been proposed. However, such method universally scales down every dimension of the devices, so the size of the gate conductor layer is shrunk, too. But, the size of the gate conductor layer is closely related to the performance of the device. The change of the size of the gate conductor layer means the change of the performance of the device, too. Such change may possibly make the device no longer workable due to the excessive deviation of the performance of the device.
Although the current method directly scales down an original IC layout, it also changes the electronic characteristics of the device and may possibly make the device no longer workable. Consequently, a novel method is needed to scale down an integrated circuit layout without substantially jeopardizing the electronic characteristics of devices involved.